/**
 * @file    gt9881_spi.h
 * @author  Giantec-Semi ATE
 * @brief   CMSIS GT98xx Device Peripheral Access Layer Header File
 * @version 0.1
 * 
 * @copyright Copyright (c) 2021 Giantec-Semi
 * 
 */

#ifndef GT98XX_DEVICE_GT9881_SPI_H_
#define GT98XX_DEVICE_GT9881_SPI_H_

#ifdef __cplusplus
  extern "C" {
#endif /* __cplusplus */

#include "gt9881.h"

/**
 * @addtogroup Peripheral_Registers_Structures
 * @{
 */

/**
 * @struct SpiTypedef
 * @brief  SPI registers structure define
 */
typedef struct tagSpiTypedef {
  __IO uint32_t TXREG;        ///< Transmit Data Register */
  __IO uint32_t RXREG;        ///< Receive Data Registe */
  __IO uint32_t CSTAT;        ///< Current Status Register */
  __IO uint32_t INTSTAT;      ///< Interrupt Status Register */
  __IO uint32_t INTEN;        ///< Interrupt Enable Register */
  __IO uint32_t INTCLR;       ///< Interrupt Clear Register */
  __IO uint32_t GCTL;         ///< Global Control Register */
  __IO uint32_t CCTL;         ///< Common Control Register */
  __IO uint32_t SPBRG;        ///< Baud Rate Generator */
  __IO uint32_t RXDNR;        ///< Receive Data Number Register */
  __IO uint32_t TXDNR;        ///< Transmit Data Number Register */
  __IO uint32_t SCSR;         ///< Slave Chip Select Register */
} SpiTypedef;
/** @} Peripheral_Registers_Structures */

/**
 * @addtogroup Peripheral_Memory_Map
 * @{
 */
#define SPI1_BASE             (PERIPH_BASE + 0x5000UL)      ///< SPI1 base address
#define SPI2_BASE             (PERIPH_BASE + 0x6000UL)      ///< SPI2 base address
/** @} Peripheral_Memory_Map */

/**
 * @addtogroup Peripheral_Declaration
 * @{
 */
#define SPI1                  ((SpiTypedef*)SPI1_BASE)      ///< SPI operator
#define SPI2                  ((SpiTypedef*)SPI2_BASE)      ///< SPI operator
/** @} Peripheral_Declaration */

/**
 * @defgroup SPI_Bitmap SPI Bitmap
 * @ingroup  Peripheral_Registers_Bits_Definition
 * @brief    Bitmap of SPI registers
 * @{
 */

#define SPI_TXREG_TXDATA_Pos                    (0U)    ///< Position of SPI_TXREG_TXDATA
#define SPI_TXREG_TXDATA_Msk                    (0xFFFFFFFFUL << SPI_TXREG_TXDATA_Pos)    ///< Bitmask of SPI_TXREG_TXDATA
/**
 * @def   SPI_TXREG_TXDATA
 * @brief The register contains the next complete data byte to transmit FIFO
 */
#define SPI_TXREG_TXDATA                        SPI_TXREG_TXDATA_Msk

#define SPI_RXREG_RXDATA_Pos                    (0U)    ///< Position of SPI_RXREG_RXDATA
#define SPI_RXREG_RXDATA_Msk                    (0xFFFFFFFFUL << SPI_RXREG_RXDATA_Pos)    ///< Bitmask of SPI_RXREG_RXDATA
/**
 * @def   SPI_RXREG_RXDATA
 * @brief The register contains the byte value of receiver FIFO
 */
#define SPI_RXREG_RXDATA                        SPI_RXREG_RXDATA_Msk

#define SPI_CSTAT_TXEPT_Pos                     (0U)    ///< Position of SPI_CSTAT_TXEPT
#define SPI_CSTAT_TXEPT_Msk                     (0x1UL << SPI_CSTAT_TXEPT_Pos)    ///< Bitmask of SPI_CSTAT_TXEPT
 /**
 * @def   SPI_CSTAT_TXEPT
 * @brief Transmitter empty bit
 * <pre>
 * @a 1'b0 : Transmitter not empty
 * @a 1'b1 : Transmitter FIFO and TX shift register are empty
 * </pre>
 */
#define SPI_CSTAT_TXEPT                         SPI_CSTAT_TXEPT_Msk

#define SPI_CSTAT_RXAVL_Pos                     (1U)    ///< Position of SPI_CSTAT_RXAVL
#define SPI_CSTAT_RXAVL_Msk                     (0x1UL << SPI_CSTAT_RXAVL_Pos)    ///< Bitmask of SPI_CSTAT_RXAVL
 /**
 * @def   SPI_CSTAT_RXAVL
 * @brief The bit is set when Receiver FIFO has received a complete word data
 * <pre>
 * @a 1'b0 : Receiver FIFO empty
 * @a 1'b1 : Receiver FIFO has a complete available word data
 * </pre>
 */
#define SPI_CSTAT_RXAVL                         SPI_CSTAT_RXAVL_Msk

#define SPI_CSTAT_TXFULL_Pos                    (2U)    ///< Position of SPI_CSTAT_TXFULL
#define SPI_CSTAT_TXFULL_Msk                    (0x1UL << SPI_CSTAT_TXFULL_Pos)   ///< Bitmask of SPI_CSTAT_TXFULL
 /**
 * @def   SPI_CSTAT_TXFULL
 * @brief Transmitter FIFO Full Status bit
 * <pre>
 * @a 1'b0 : Transmitter FIFO is not full
 * @a 1'b1 : Transmitter FIFO is full
 * </pre>
 */
#define SPI_CSTAT_TXFULL                        SPI_CSTAT_TXFULL_Msk


#define SPI_CSTAT_RXAVL_4_Pos                   (3U)    ///< Position of SPI_CSTAT_RXAVL_4
#define SPI_CSTAT_RXAVL_4_Msk                   (0x1UL << SPI_CSTAT_RXAVL_4_Pos)    ///< Bitmask of SPI_CSTAT_RXAVL_4
 /**
 * @def   SPI_CSTAT_RXAVL_4
 * @brief The bit is set when Receiver FIFO has received more than 4 avaliable data.
 * <pre>
 * @a 1'b0 : Receiver FIFO empty
 * @a 1'b1 : Receiver FIFO has more than 4 avaliable data
 * </pre>
 */
#define SPI_CSTAT_RXAVL_4                       SPI_CSTAT_RXAVL_4_Msk

#define SPI_INTSTAT_TXINTF_Pos                  (0U)    ///< Position of SPI_INTSTAT_TXINTF
#define SPI_INTSTAT_TXINTF_Msk                  (0x1UL << SPI_INTSTAT_TXINTF_Pos)   ///< Bitmask of SPI_INTSTAT_TXINTF
 /**
 * @def   SPI_INTSTAT_TXINTF
 * @brief Transmit FIFO available interrupt flag bit (depend on txtlf)
 * <pre>
 * @a 1'b0 : Transmitter FIFO is not available
 * @a 1'b1 : Transmitter FIFO is available
 * </pre>
 */
#define SPI_INTSTAT_TXINTF                      SPI_INTSTAT_TXINTF_Msk

#define SPI_INTSTAT_RXINTF_Pos                  (1U)    ///< Position of SPI_INTSTAT_RXINTF
#define SPI_INTSTAT_RXINTF_Msk                  (0x1UL << SPI_INTSTAT_RXINTF_Pos)   ///< Bitmask of SPI_INTSTAT_RXINTF
 /**
 * @def   SPI_INTSTAT_RXINTF
 * @brief Receiver data available interrupt flag bit. (depend on rxtlf)
 * <pre>
 * @a 1'b0 : Receiver FIFO not available
 * @a 1'b1 : Receiver FIFO has available data
 * </pre>
 */
#define SPI_INTSTAT_RXINTF                      SPI_INTSTAT_RXINTF_Msk

#define SPI_INTSTAT_UNDERRUNINTF_Pos            (2U)    ///< Position of SPI_INTSTAT_UNDERRUNINTF
#define SPI_INTSTAT_UNDERRUNINTF_Msk            (0x1UL << SPI_INTSTAT_UNDERRUNINTF_Pos)   ///< Bitmask of SPI_INTSTAT_UNDERRUNINTF
 /**
 * @def   SPI_INTSTAT_UNDERRUNINTF
 * @brief SPI slave transmitter underrun flag bit
 * <pre>
 * @a 1'b0 : No underrun error
 * @a 1'b1 : Underrun error
 * </pre>
 */
#define SPI_INTSTAT_UNDERRUNINTF                SPI_INTSTAT_UNDERRUNINTF_Msk

#define SPI_INTSTAT_RXOERRINTF_Pos              (3U)    ///< Position of SPI_INTSTAT_RXOERRINTF
#define SPI_INTSTAT_RXOERRINTF_Msk              (0x1UL << SPI_INTSTAT_RXOERRINTF_Pos)   ///< Bitmask of SPI_INTSTAT_RXOERRINTF
 /**
 * @def   SPI_INTSTAT_RXOERRINTF
 * @brief Receiver Overrun Error interrupt Flag bit
 * <pre>
 * @a 1'b0 : No overrun error
 * @a 1'b1 : Overrun error
 * </pre>
 */
#define SPI_INTSTAT_RXOERRINTF                  SPI_INTSTAT_RXOERRINTF_Msk

#define SPI_INTSTAT_RXMATCHINTF_Pos             (4U)    ///< Position of SPI_INTSTAT_RXMATCHINTF
#define SPI_INTSTAT_RXMATCHINTF_Msk             (0x1UL << SPI_INTSTAT_RXMATCHINTF_Pos)    ///< Bitmask of SPI_INTSTAT_RXMATCHINTF
 /**
 * @def   SPI_INTSTAT_RXMATCHINTF
 * @brief The bit is set when SPI master completes a receive task and SPI slave completes a receive task
 */
#define SPI_INTSTAT_RXMATCHINTF                 SPI_INTSTAT_RXMATCHINTF_Msk

#define SPI_INTSTAT_RXFIFOFULLINTF_Pos          (5U)    ///< Position of SPI_INTSTAT_RXFIFOFULLINTF
#define SPI_INTSTAT_RXFIFOFULLINTF_Msk          (0x1UL << SPI_INTSTAT_RXFIFOFULLINTF_Pos)   ///< Bitmask of SPI_INTSTAT_RXFIFOFULLINTF
 /**
 * @def   SPI_INTSTAT_RXFIFOFULLINTF
 * @brief RX FIFO Full interrupt flag bit
 * <pre>
 * @a 1'b0 : Receive FIFO not full
 * @a 1'b1 : Receive FIFO full
 * </pre>
 */
#define SPI_INTSTAT_RXFIFOFULLINTF              SPI_INTSTAT_RXFIFOFULLINTF_Msk

#define SPI_INTSTAT_TXEPTINTF_Pos               (6U)    ///< Position of SPI_INTSTAT_TXEPTINTF
#define SPI_INTSTAT_TXEPTINTF_Msk               (0x1UL << SPI_INTSTAT_TXEPTINTF_Pos)    ///< Bitmask of SPI_INTSTAT_TXEPTINTF
 /**
 * @def   SPI_INTSTAT_TXEPTINTF
 * @brief Transmitter empty interrupt flag bit.
 * <pre>
 * @a 1'b0 : Transmitter FIFO and TX shift register are empty
 * @a 1'b1 : Transmitter not empty
 * </pre>
 */
#define SPI_INTSTAT_TXEPTINTF                   SPI_INTSTAT_TXEPTINTF_Msk

#define SPI_INTSTAT_TXMATCHINTF_Pos             (7U)    ///< Position of SPI_INTSTAT_TXMATCHINTF
#define SPI_INTSTAT_TXMATCHINTF_Msk             (0x1UL << SPI_INTSTAT_TXMATCHINTF_Pos)    ///< Bitmask of SPI_INTSTAT_TXMATCHINTF
 /**
 * @def   SPI_INTSTAT_TXMATCHINTF
 * @brief The bit is set when SPI master completes a transmit task or and SPI slave completes a transmit task
 */
#define SPI_INTSTAT_TXMATCHINTF                 SPI_INTSTAT_TXMATCHINTF_Msk

#define SPI_INTENA_TXIEN_Pos                    (0U)    ///< Position of SPI_INTENA_TXIEN
#define SPI_INTENA_TXIEN_Msk                    (0x1UL << SPI_INTENA_TXIEN_Pos)   ///< Bitmask of SPI_INTENA_TXIEN
 /**
 * @def   SPI_INTENA_TXIEN
 * @brief Transmitter FIFO empty interrupt enable bit.
 * <pre>
 * @a 1'b0 : Interrupt not enable
 * @a 1'b1 : Interrupt enabled
 * </pre>
 */
#define SPI_INTENA_TXIEN                        SPI_INTENA_TXIEN_Msk

#define SPI_INTENA_RXIEN_Pos                    (1U)    ///< Position of SPI_INTENA_RXIEN
#define SPI_INTENA_RXIEN_Msk                    (0x1UL << SPI_INTENA_RXIEN_Pos)   ///< Bitmask of SPI_INTENA_RXIEN
 /**
 * @def   SPI_INTENA_RXIEN
 * @brief Receiver FIFO interrupt enable bit
 * <pre>
 * @a 1'b0 : Interrupt not enable
 * @a 1'b1 : Interrupt enabled
 * </pre>
 */
#define SPI_INTENA_RXIEN                        SPI_INTENA_RXIEN_Msk

#define SPI_INTENA_UNDERRUNEN_Pos               (2U)    ///< Position of SPI_INTENA_UNDERRUNEN
#define SPI_INTENA_UNDERRUNEN_Msk               (0x1UL << SPI_INTENA_UNDERRUNEN_Pos)    ///< Bitmask of SPI_INTENA_UNDERRUNEN
 /**
 * @def   SPI_INTENA_UNDERRUNEN
 * @brief Transmitter underrun interrupt enable bit (SPI slave mode only)
 * <pre>
 * @a 1'b0 : Interrupt not enable
 * @a 1'b1 : Interrupt enabled
 * </pre>
 */
#define SPI_INTENA_UNDERRUNEN                   SPI_INTENA_UNDERRUNEN_Msk

#define SPI_INTENA_RXOERREN_Pos                 (3U)    ///< Position of SPI_INTENA_RXOERREN
#define SPI_INTENA_RXOERREN_Msk                 (0x1UL << SPI_INTENA_RXOERREN_Pos)    ///< Bitmask of SPI_INTENA_RXOERREN
 /**
 * @def   SPI_INTENA_RXOERREN
 * @brief Overrun Error interrupt enable bit
 * <pre>
 * @a 1'b0 : Interrupt not enable
 * @a 1'b1 : Interrupt enabled
 * </pre>
 */
#define SPI_INTENA_RXOERREN                     SPI_INTENA_RXOERREN_Msk

#define SPI_INTENA_RXMATCHEN_Pos                (4U)    ///< Position of SPI_INTENA_RXMATCHEN
#define SPI_INTENA_RXMATCHEN_Msk                (0x1UL << SPI_INTENA_RXMATCHEN_Pos)   ///< Bitmask of SPI_INTENA_RXMATCHEN
 /**
 * @def   SPI_INTENA_RXMATCHEN
 * @brief Receive data complete interrupt signal.
 * <pre>
 * @a 1'b0 : Interrupt not enable
 * @a 1'b1 : Interrupt enabled
 * </pre>
 */
#define SPI_INTENA_RXMATCHEN                    SPI_INTENA_RXMATCHEN_Msk

#define SPI_INTENA_RX_FIFIOFULL_IEN_Pos         (5U)    ///< Position of SPI_INTENA_RX_FIFIOFULL_IEN
#define SPI_INTENA_RX_FIFIOFULL_IEN_Msk         (0x1UL << SPI_INTENA_RX_FIFIOFULL_IEN_Pos)    ///< Bitmask of SPI_INTENA_RX_FIFIOFULL_IEN
 /**
 * @def   SPI_INTENA_RX_FIFIOFULL_IEN
 * @brief Receiver FIFO Full interrupt enable bit.
 * <pre>
 * @a 1'b0 : Interrupt not enable
 * @a 1'b1 : Interrupt enabled
 * </pre>
 */
#define SPI_INTENA_RX_FIFIOFULL_IEN             SPI_INTENA_RX_FIFIOFULL_IEN_Msk

#define SPI_INTENA_TXEPT_IEN_Pos                (6U)    ///< Position of SPI_INTENA_TXEPT_IEN
#define SPI_INTENA_TXEPT_IEN_Msk                (0x1UL << SPI_INTENA_TXEPT_IEN_Pos)   ///< Bitmask of SPI_INTENA_TXEPT_IEN
 /**
 * @def   SPI_INTENA_TXEPT_IEN
 * @brief Trasnmit empty interrupt enable bit
 * <pre>
 * @a 1'b0 : Interrupt not enable
 * @a 1'b1 : Interrupt enabled
 * </pre>
 */
#define SPI_INTENA_TXEPT_IEN                    SPI_INTENA_TXEPT_IEN_Msk

#define SPI_INTENA_TXMATCHEN_Pos                (7U)    ///< Position of SPI_INTENA_TXMATCHEN
#define SPI_INTENA_TXMATCHEN_Msk                (0x1UL << SPI_INTENA_TXMATCHEN_Pos)   ///< Bitmask of SPI_INTENA_TXMATCHEN
 /**
 * @def   SPI_INTENA_TXMATCHEN
 * @brief Transmit data complete interrupt signal.
 * <pre>
 * @a 1'b0 : Interrupt not enable
 * @a 1'b1 : Interrupt enabled
 * </pre>
 */
#define SPI_INTENA_TXMATCHEN                    SPI_INTENA_TXMATCHEN_Msk

#define SPI_INTCLR_TXICLR_Pos                   (0U)    ///< Position of SPI_INTCLR_TXICLR
#define SPI_INTCLR_TXICLR_Msk                   (0x1UL << SPI_INTCLR_TXICLR_Pos)    ///< Bitmask of SPI_INTCLR_TXICLR
 /**
 * @def   SPI_INTCLR_TXICLR
 * @brief Transmitter FIFO empty interrupt clear bit
 * <pre>
 * @a 1'b0 : Interrupt not cleared
 * @a 1'b1 : Interrupt
 * </pre>
 */
#define SPI_INTCLR_TXICLR                       SPI_INTCLR_TXICLR_Msk

#define SPI_INTCLR_RXICLR_Pos                   (1U)    ///< Position of SPI_INTCLR_RXICLR
#define SPI_INTCLR_RXICLR_Msk                   (0x1UL << SPI_INTCLR_RXICLR_Pos)    ///< Bitmask of SPI_INTCLR_RXICLR
 /**
 * @def   SPI_INTCLR_RXICLR
 * @brief Receiver interrupt clear bit
 * <pre>
 * @a 1'b0 : Interrupt not cleared
 * @a 1'b1 : Interrupt cleared
 * </pre>
 */
#define SPI_INTCLR_RXICLR                       SPI_INTCLR_RXICLR_Msk

#define SPI_INTCLR_UNDERRUNCLR_Pos              (2U)    ///< Position of SPI_INTCLR_UNDERRUNCLR
#define SPI_INTCLR_UNDERRUNCLR_Msk              (0x1UL << SPI_INTCLR_UNDERRUNCLR_Pos)   ///< Bitmask of SPI_INTCLR_UNDERRUNCLR
 /**
 * @def   SPI_INTCLR_UNDERRUNCLR
 * @brief Transmitter underrun interrupt clear bit (SPI slave mode only)
 * <pre>
 * @a 1'b0 : Interrupt not cleared
 * @a 1'b1 : Interrupt cleared
 * </pre>
 */
#define SPI_INTCLR_UNDERRUNCLR                  SPI_INTCLR_UNDERRUNCLR_Msk

#define SPI_INTCLR_RXOERRCLR_Pos                (3U)    ///< Position of SPI_INTCLR_RXOERRCLR
#define SPI_INTCLR_RXOERRCLR_Msk                (0x1UL << SPI_INTCLR_RXOERRCLR_Pos)   ///< Bitmask of SPI_INTCLR_RXOERRCLR
 /**
 * @def   SPI_INTCLR_RXOERRCLR
 * @brief Overrun Error interrupt clear bit
 * <pre>
 * @a 1'b0 : Interrupt not cleared
 * @a 1'b1 : Interrupt cleared
 * </pre>
 */
#define SPI_INTCLR_RXOERRCLR                    SPI_INTCLR_RXOERRCLR_Msk

#define SPI_INTCLR_RXMATCHCLR_Pos               (4U)    ///< Position of SPI_INTCLR_RXMATCHCLR
#define SPI_INTCLR_RXMATCHCLR_Msk               (0x1UL << SPI_INTCLR_RXMATCHCLR_Pos)    ///< Bitmask of SPI_INTCLR_RXMATCHCLR
 /**
 * @def   SPI_INTCLR_RXMATCHCLR
 * @brief Receive completed interrupt clear bit
 * <pre>
 * @a 1'b0 : Interrupt not cleared
 * @a 1'b1 : Interrupt cleared
 * </pre>
 */
#define SPI_INTCLR_RXMATCHCLR                   SPI_INTCLR_RXMATCHCLR_Msk

#define SPI_INTCLR_RXFIFO_FULL_ICLR_Pos         (5U)    ///< Position of SPI_INTCLR_RXFIFO_FULL_ICLR
#define SPI_INTCLR_RXFIFO_FULL_ICLR_Msk         (0x1UL << SPI_INTCLR_RXFIFO_FULL_ICLR_Pos)    ///< Bitmask of SPI_INTCLR_RXFIFO_FULL_ICLR
 /**
 * @def   SPI_INTCLR_RXFIFO_FULL_ICLR
 * @brief Receiver FIFO Full interrupt clear bit.
 * <pre>
 * @a 1'b0 : Interrupt not cleared
 * @a 1'b1 : Interrupt cleared
 * </pre>
 */
#define SPI_INTCLR_RXFIFO_FULL_ICLR             SPI_INTCLR_RXFIFO_FULL_ICLR_Msk

#define SPI_INTCLR_TXEPT_ICLR_Pos               (6U)    ///< Position of SPI_INTCLR_TXEPT_ICLR
#define SPI_INTCLR_TXEPT_ICLR_Msk               (0x1UL << SPI_INTCLR_TXEPT_ICLR_Pos)    ///< Bitmask of SPI_INTCLR_TXEPT_ICLR
 /**
 * @def   SPI_INTCLR_TXEPT_ICLR
 * @brief Transmitter empty interrupt clear bit
 * <pre>
 * @a 1'b0 : Interrupt not cleared
 * @a 1'b1 : Interrupt cleared
 * </pre>
 */
#define SPI_INTCLR_TXEPT_ICLR                   SPI_INTCLR_TXEPT_ICLR_Msk

#define SPI_INTCLR_TXMATCHCLR_Pos               (7U)    ///< Position of SPI_INTCLR_TXMATCHCLR
#define SPI_INTCLR_TXMATCHCLR_Msk               (0x1UL << SPI_INTCLR_TXMATCHCLR_Pos)    ///< Bitmask of SPI_INTCLR_TXMATCHCLR
 /**
 * @def   SPI_INTCLR_TXMATCHCLR
 * @brief Transmit completed interrupt clear bit
 * <pre>
 * @a 1'b0 : Interrupt not cleared
 * @a 1'b1 : Interrupt cleared
 * </pre>
 */
#define SPI_INTCLR_TXMATCHCLR                   SPI_INTCLR_TXMATCHCLR_Msk

#define SPI_GCTL_SPIEN_Pos                      (0U)    ///< Position of SPI_GCTL_SPIEN
#define SPI_GCTL_SPIEN_Msk                      (0x1UL << SPI_GCTL_SPIEN_Pos)   ///< Bitmask of SPI_GCTL_SPIEN
 /**
 * @def   SPI_GCTL_SPIEN
 * @brief SPI select bits
 * <pre>
 * @a 1'b0 : SPI disable (held in Reset)
 * @a 1'b1 : SPI enable
 * </pre>
 */
#define SPI_GCTL_SPIEN                          SPI_GCTL_SPIEN_Msk

#define SPI_GCTL_INTEN_Pos                      (1U)    ///< Position of SPI_GCTL_INTEN
#define SPI_GCTL_INTEN_Msk                      (0x1UL << SPI_GCTL_INTEN_Pos)   ///< Bitmask of SPI_GCTL_INTEN
 /**
 * @def   SPI_GCTL_INTEN
 * @brief SPI interrupt enable bit
 * <pre>
 * @a 1'b0 : Disable SPI interrupt
 * @a 1'b1 : Enable SPI interrupt
 * </pre>
 */
#define SPI_GCTL_INTEN                          SPI_GCTL_INTEN_Msk

#define SPI_GCTL_MM_Pos                         (2U)    ///< Position of SPI_GCTL_MM
#define SPI_GCTL_MM_Msk                         (0x1UL << SPI_GCTL_MM_Pos)    ///< Bitmask of SPI_GCTL_MM
 /**
 * @def   SPI_GCTL_MM
 * @brief Master Mode bit
 * <pre>
 * @a 1'b0 : Slave mode (Clock from external source)
 * @a 1'b1 : Master mode (Clock generated internally from BRG)
 * </pre>
 */
#define SPI_GCTL_MM                             SPI_GCTL_MM_Msk

#define SPI_GCTL_TXEN_Pos                       (3U)    ///< Position of SPI_GCTL_TXEN
#define SPI_GCTL_TXEN_Msk                       (0x1UL << SPI_GCTL_TXEN_Pos)    ///< Bitmask of SPI_GCTL_TXEN
 /**
 * @def   SPI_GCTL_TXEN
 * @brief Transmit Enable bit
 * <pre>
 * @a 1'b0 : Transmit disabled. It can clear Transmitter FIFO
 * @a 1'b1 : Transmit enabled
 * </pre>
 */
#define SPI_GCTL_TXEN                           SPI_GCTL_TXEN_Msk

#define SPI_GCTL_RXEN_Pos                       (4U)    ///< Position of SPI_GCTL_RXEN
#define SPI_GCTL_RXEN_Msk                       (0x1UL << SPI_GCTL_RXEN_Pos)    ///< Bitmask of SPI_GCTL_RXEN
 /**
 * @def   SPI_GCTL_RXEN
 * @brief Receive Enable bit
 * <pre>
 * @a 1'b0 : Disable receive. It can clear Receiver FIFO.
 * @a 1'b1 : Enable receive
 * </pre>
 */
#define SPI_GCTL_RXEN                           SPI_GCTL_RXEN_Msk

#define SPI_GCTL_RXTLF_Pos                      (5U)    ///< Position of SPI_GCTL_RXTLF
#define SPI_GCTL_RXTLF_Msk                      (0x3UL << SPI_GCTL_RXTLF_Pos)   ///< Bitmask of SPI_GCTL_RXTLF
 /**
 * @def   SPI_GCTL_RXTLF
 * @brief RX FIFO trigger level bit
 * <pre>
 * @a 2'b00 : One or more valid data in RX FIFO
 * @a 2'b01 : more than 4 data in RX FIFO
 * @a 2'b10 : more than 8 data in RX FIFO
 * @a 2'b11 : more than 16 data in RX FIFO
 * </pre>
 */
#define SPI_GCTL_RXTLF                          SPI_GCTL_RXTLF_Msk

#define SPI_GCTL_TXTLF_Pos                      (7U)    ///< Position of SPI_GCTL_TXTLF
#define SPI_GCTL_TXTLF_Msk                      (0x3UL << SPI_GCTL_TXTLF_Pos)   ///< Bitmask of SPI_GCTL_TXTLF
 /**
 * @def   SPI_GCTL_TXTLF
 * @brief TX FIFO trigger level bit
 * <pre>
 * @a 2'b00 : one or more valid space in TX FIFO
 * @a 2'b01 : 4 or more valid space in TX FIFO
 * @a 2'b10 : 8 or more valid space in TX FIFO
 * @a 2'b11 : 16 or more valid space in TX FIFO
 * </pre>
 */
#define SPI_GCTL_TXTLF                          SPI_GCTL_TXTLF_Msk

#define SPI_GCTL_DMAMODE_Pos                    (9U)    ///< Position of SPI_GCTL_DMAMODE
#define SPI_GCTL_DMAMODE_Msk                    (0x1UL << SPI_GCTL_DMAMODE_Pos)   ///< Bitmask of SPI_GCTL_DMAMODE
 /**
 * @def   SPI_GCTL_DMAMODE
 * @brief DMA access mode bit
 * <pre>
 * @a 1'b0 : normal access mode (Only CPU access TX FIFO and RX FIFO)
 * @a 1'b1 : DMA access mode (Only DMA access TX FIFO and RX FIFO)
 * </pre>
 */
#define SPI_GCTL_DMAMODE                        SPI_GCTL_DMAMODE_Msk

#define SPI_GCTL_SIMPLEX_MODE_Pos               (15U)   ///< Position of SPI_GCTL_SIMPLEX_MODE
#define SPI_GCTL_SIMPLEX_MODE_Msk               (0x1UL << SPI_GCTL_SIMPLEX_MODE_Pos)    ///< Bitmask of SPI_GCTL_SIMPLEX_MODE
 /**
 * @def   SPI_GCTL_SIMPLEX_MODE
 * @brief Simplex mode
 * <pre>
 * @a 1'b0 : normal mode
 * @a 1'b1 : simplex mode
 * </pre>
 */
#define SPI_GCTL_SIMPLEX_MODE                   SPI_GCTL_SIMPLEX_MODE_Msk

#define SPI_GCTL_3WIRE_BUS_Pos                  (16U)   ///< Position of SPI_GCTL_3WIRE_BUS
#define SPI_GCTL_3WIRE_BUS_Msk                  (0x1UL << SPI_GCTL_3WIRE_BUS_Pos)   ///< Bitmask of SPI_GCTL_3WIRE_BUS
 /**
 * @def   SPI_GCTL_3WIRE_BUS
 * @brief 3 wire mode
 * <pre>
 * @a 1'b0 : 4 wire bus
 * @a 1'b1 : 3 wire bus
 * </pre>
 */
#define SPI_GCTL_3WIRE_BUS                      SPI_GCTL_3WIRE_BUS_Msk

#define SPI_GCTL_MONITOR_MODE_Pos               (17U)   ///< Position of SPI_GCTL_MONITOR_MODE
#define SPI_GCTL_MONITOR_MODE_Msk               (0x1UL << SPI_GCTL_MONITOR_MODE_Pos)    ///< Bitmask of SPI_GCTL_MONITOR_MODE
 /**
 * @def   SPI_GCTL_MONITOR_MODE
 * @brief Monitor mode
 * <pre>
 * @a 1'b0 : monitor off
 * @a 1'b1 : monitor on
 * </pre>
 */
#define SPI_GCTL_MONITOR_MODE                   SPI_GCTL_MONITOR_MODE_Msk

#define SPI_CCTL_CKPH_Pos                       (0U)    ///< Position of SPI_CCTL_CKPH
#define SPI_CCTL_CKPH_Msk                       (0x1UL << SPI_CCTL_CKPH_Pos)    ///< Bitmask of SPI_CCTL_CKPH
 /**
 * @def   SPI_CCTL_CKPH
 * @brief Clock Phase Select bit
 */
#define SPI_CCTL_CKPH                           SPI_CCTL_CKPH_Msk

#define SPI_CCTL_CKPL_Pos                       (1U)    ///< Position of SPI_CCTL_CKPL
#define SPI_CCTL_CKPL_Msk                       (0x1UL << SPI_CCTL_CKPL_Pos)    ///< Bitmask of SPI_CCTL_CKPL
 /**
 * @def   SPI_CCTL_CKPL
 * @brief SPI Clock Polarity Select bit. It selects an inverted or non-inverted SPI clock.
 * <pre>
 * @a 1'b0 : Active-high clocks selected. In idle state SCLK is low.
 * @a 1'b1 : Active-low clocks selected. In idle state SCLK is high.
 * </pre>
 */
#define SPI_CCTL_CKPL                           SPI_CCTL_CKPL_Msk

#define SPI_CCTL_LSBFE_Pos                      (2U)    ///< Position of SPI_CCTL_LSBFE
#define SPI_CCTL_LSBFE_Msk                      (0x1UL << SPI_CCTL_LSBFE_Pos)   ///< Bitmask of SPI_CCTL_LSBFE
 /**
 * @def   SPI_CCTL_LSBFE
 * @brief SPI Clock Polarity Select bit. It selects an inverted or non-inverted SPI clock.
 * <pre>
 * @a 1'b0 : Data is transferred or received most significant bit(MSB) first
 * @a 1'b1 : Data is transferred or received least significant bit (LSB) first
 * </pre>
 */
#define SPI_CCTL_LSBFE                          SPI_CCTL_LSBFE_Msk

#define SPI_CCTL_RXEDGE_Pos                     (4U)    ///< Position of SPI_CCTL_RXEDGE
#define SPI_CCTL_RXEDGE_Msk                     (0x1UL << SPI_CCTL_RXEDGE_Pos)    ///< Bitmask of SPI_CCTL_RXEDGE
 /**
 * @def   SPI_CCTL_RXEDGE
 * @brief Master mode rx data sample edge select
 * <pre>
 * @a 1'b0 : sample the middle of the rxed data,low speed use
 * @a 1'b1 : sample the edge of the rxed data, high speed use
 * </pre>
 */
#define SPI_CCTL_RXEDGE                         SPI_CCTL_RXEDGE_Msk

#define SPI_CCTL_SPILEN_Pos                     (8U)    ///< Position of SPI_CCTL_SPILEN
#define SPI_CCTL_SPILEN_Msk                     (0x1FUL << SPI_CCTL_SPILEN_Pos)   ///< Bitmask of SPI_CCTL_SPILEN
 /**
 * @def   SPI_CCTL_SPILEN
 * @brief SPI length bits(ti_mode only support 4to31 bit)
 * <pre>
 * @a 0~2  : Reserved
 * @a 3~15 : 4~16 bit mode
 * </pre>
 */
#define SPI_CCTL_SPILEN                         SPI_CCTL_SPILEN_Msk

#define SPI_SPBRG_BAUDRATE_Pos                  (0U)    ///< Position of SPI_SPBRG_BAUDRATE
#define SPI_SPBRG_BAUDRATE_Msk                  (0xFFFFUL << SPI_SPBRG_BAUDRATE_Pos)    ///< Bitmask of SPI_SPBRG_BAUDRATE
 /**
 * @def   SPI_SPBRG_BAUDRATE
 * @brief The SPI Baud Rate Control register for baud rate.
 * <pre>
 * Baud Rate = fpclk / SPBRG
 * </pre>
 */
#define SPI_SPBRG_BAUDRATE                      SPI_SPBRG_BAUDRATE_Msk

#define SPI_RXDNR_RXDATA_NUM_Pos                (0U)    ///< Position of SPI_RXDNR_RXDATA_NUM
#define SPI_RXDNR_RXDATA_NUM_Msk                (0xFFFFUL << SPI_RXDNR_RXDATA_NUM_Pos)    ///< Bitmask of SPI_RXDNR_RXDATA_NUM
 /**
 * @def   SPI_RXDNR_RXDATA_NUM
 * @brief Hold a count of to be received beats in next receive process.
 * <pre>
 * SPI Master Mode : valid in SPI master single receive mode (simplex mode) or 3wire mode
 * SPI Slave Mode  : The register is valid in both simplex mode and duplex mode.
 * Don't write "0" to the register.
 * </pre>
 */
#define SPI_RXDNR_RXDATA_NUM                    SPI_RXDNR_RXDATA_NUM_Msk

#define SPI_TXDNR_TXDATA_NUM_Pos                (0U)    ///< Position of SPI_TXDNR_TXDATA_NUM
#define SPI_TXDNR_TXDATA_NUM_Msk                (0xFFFFUL << SPI_TXDNR_TXDATA_NUM_Pos)    ///< Bitmask of SPI_TXDNR_TXDATA_NUM
 /**
 * @def   SPI_TXDNR_TXDATA_NUM
 * @brief Hold a count of to be transmited beats in next transmitter process.
 * <pre>
 * SPI Master Mode : The register is valid in both simplex mode and duplex mode
 * SPI Slave Mode  : The register is only valid in simplex mode.
 * Don't write "0" to the register.
 * </pre>
 */
#define SPI_TXDNR_TXDATA_NUM                    SPI_TXDNR_TXDATA_NUM_Msk

#define SPI_SCSR_CSN_Pos                        (0U)    ///< Position of SPI_SCSR_CSN
#define SPI_SCSR_CSN_Msk                        (0xFFUL << SPI_SCSR_CSN_Pos)    ///< Bitmask of SPI_SCSR_CSN
 /**
 * @def   SPI_SCSR_CSN
 * @brief Chip select output signal in Master mode.
 * <pre>
 * @a 1'b0 : Slave selected
 * @a 1'b1 : Slave not selected
 * Support 8 slave SPI device from 0~7
 * </pre>
 */
#define SPI_SCSR_CSN                            SPI_SCSR_CSN_Msk

/** @} SPI_Bitmap */

/**
 * @addtogroup Exported_Macros
 * @{
 */

/**
 * @def   IS_SPI_ALL_INSTANCE
 * @brief Check if INSTANCE is SPI instance
 */
#define IS_SPI_ALL_INSTANCE(INSTANCE)         (((INSTANCE) == SPI1) || \
                                               ((INSTANCE) == SPI2))

/** @} Exported_Macros */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* GT98XX_DEVICE_GT9881_SPI_H_ */
